Integrated circuit capacitors are widely used in integrated circuit devices. For example, in Dynamic Random Access Memory (DRAM) devices, integrated circuit capacitors may be used to store charge thereon and thereby store data. As the integration density of DRAM devices continues to increase, it is desirable to maintain sufficiently high storage capacitance while decreasing the area of an integrated circuit substrate that is occupied by each capacitor.
When the integration density of the integrated circuit capacitors is increased, it may become more difficult to align the capacitor lower electrode, also referred to as a storage node, to an underlying contact hole. Moreover, in order to allow relatively high capacitance while decreasing the substrate surface area of the capacitor, the height of the storage node may increase as the area decreases. For example the height of the storage node may increase to one micron or more in a stacked capacitor structure. This may result in a high aspect ratio of the storage node, for example an aspect ratio exceeding 5. This high aspect ratio may make it difficult to pattern a thick conductive layer to form the storage nodes.
A conventional process for stacked capacitor formation is described as follows. An insulating layer is formed over a semiconductor substrate. A contact is opened in the insulating layer to an active region of the semiconductor substrate and conductive material is deposited in the contact opening to form a contact plug. A thick conductive layer is deposited on the insulating layer including the contact plug. Anisotropic etching is carried to etch the thick conductive layer between each contact plug and thereby to form a stacked capacitor. Overetching is conventionally carried out after main etching of the thick conductive layer to obtain etching uniformity and avoid micro bridge between each storage node and the next.
Unfortunately, during anisotropic etching of the storage node, lateral etching may also occur, especially during the overetching process, which may cause the storage node to break. More specifically, as the etching process continues to expose the upper surface of the insulating layer, the exposed layer may be charged positively by etchant. As a result, etchant gas etches the bottom edges of the storage node to cause undercut phenomenon.